Participate
in definition and driving both chip level and block level design-for-test
methodology for SOC designs.
Responsible
for Automatic Test Pattern Generation and model creation, memory Built In Self
Test, Embedded Deterministic Test and converting scan patterns to tester
format.
Responsible
for scan pattern simulation based on timing files and gate-level netlist,
assisted backend engineer with scan chain insertion and timing analysis.
Work
closely with design engineer for design optimization for test coverage
improvement, test volume and test time reduction.
Work
closely with product and test engineers to debug and solve scan pattern
failures in tester.
Work as a
global team to do complex SOC design and test based on embedded MCU.
Qualifications:
BSEE
required
Engineering
with 0-5 years experience in Design for Test (DFT).
Relevant
project experience in design for test activities, experience using tools
including: Fastscan, Tetramax,Encounter Test, TestKompress, MBIST architect,
YieldAssist etc.
Relevant
project experience in digital designs based on verilog or VHDL, with basic
knowledge of design flow, including RTL coding, verification, synthesis, STA,
test and validation.
Relevant experience
in the area of embedded processors, MCU is a big plus.
Familiar
with ATE platform, (insert testers here) software and hardware is a strong
plus.
Familiar
with main EDA tools, such as Cadence, Mentor, Magna and Synposis.
Good grasp
of Verilog/VHDL, C/C++ and Perl/TCL scripts in Linux/Unix environment.
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